The lattice defect generation and its thermal behavior by silicon etching and oxidation were studied using a cross-sectional high resolution transmission electron microscope. Ar and $Ar/H_2$ were used as plasma etching gas sources to compare the effects on defect generation of etching gases containing hydrogen with those without hydrogen. A transmission electron microscope was used to characterize the microstructure of the above samples. Bright field and high resolution transmission electron micrographs were obtained by a JEOL JEM 2000EX electron microscope with a high resolution pole piece, operated at 200 kV. To measure the electrical properties of the silicon samples having lattice defects, current-voltage and capacitance-voltage characteristics of Schottky diodes formed on the plasma etched silicon surfaces were investigated. The plasma etched silicon wafers were annealed in a 3 zone furnace at the temperature ranges of 200~1100℃ for 30 min and oxidized in the same furnace in a $H_2O$ ambient at 900℃. As a combination of etching and oxidation, some device isolation structures like sidewalled PBLOCOS(poly-buffered local oxidation of silicon) were investigated in view of the defect generation.
Cross-sectional TEM results after Ar and $Ar/H_2$ plasma etching showed 3 different types of lattice damaged layers in silicon and also contaminations on the silicon surface were found. With the increase of bias power, the density of defects was increased, but the depth of defects decreased due to the silicon surface removal by highly biased etching ion. (111), (311), and (100) stacking faults were observed near the surface damaged by incident etching ions. Among these defects, (111) stacking faults were placed the deepest in silicon and the density of them was the highest, especially in case of $Ar/H_2$ gas etching.
The density and size of defects decreased at higher annealing temperature. In case of point defects, after 800℃ annealing for 30 min, all of them were removed. However, the stacking faults formed by plasma etching ions were not removed and especially, (111) stacking faults formed during the $Ar/H_2$ etching were not removed even after 1100℃ annealing. On the other hand, (111) stacking faults formed during the Ar etching and all of the other defects were completely removed after 900℃ annealing.
The characteristics of lattice defects in trench patterned silicon after oxidation at 900℃ were similar to those observed in the annealed silicon. Some of the lattice defects on the silicon surface were removed by oxidation of silicon containing the lattice defects. However, the lattice defects located outside of the oxidation range were reduced during the oxidation only due to the annealing effects. Lattice defects can be generated during the oxidation due to the stress concentration near the edge of the trench. And the lattice defects in silicon can promote the generation of additional defects due to the collaboration of lattice defects and silicon interstitials formed by the oxidation process. These defects can be observed near the silicon and silicon dioxide interface.
During the PBLOCOS process using the polysilicon sidewall, the polysilicon pitting phenomena was observed because of the Kooi effects near the active area corner. Lattice damage also observed in silicon below the bird's beak area. The observed defects results from the local stress concentration near the silicon edge caused by silicon nitride barrier.
