This thesis covers an implementation of digital audio processor for cellular phone applications. This chip is divided into two part, the Digital Signal Processor(DSP) core block and the digital filter block. The DSP core block uses 4 stage pipelining and performs compressing, expanding and other signal processing algorithms. The digital filter block performs preemphasis, deemphasis and low pass filtering. This chip contains the Dual Tone Multiple Frequency(DTMF) generator whose tone can be programmed via the internal serial bus interface. It uses 10MHz 4 phase clock and samples the audio signal at the rate of 10K-samples per second.
For power saving, this chip uses the low power strategy and power down mode. The experimental results of this chip show that it consumes 512.1mW at 5V and 9.3mW in power down mode.
