This thesis covers a design of execution unit and control unit for CISC type superscalar microprocessor. The execution unit has two pipelines. When two RISCore instructions which are simple and pairable instructions are issued, they are executed in each pipeline respectively. An analysis of X86 instruction set usage[11] shows that the usage frequency of the RISCore instructions is about 80%. Even though complex instructions are not pairable, they use both pipelines to reduce execution cycle time. The control unit is designed by microprogrammed approach. The control storage is constructed with two separated ROMs for each pipeline.
Design verification is an important part of processor design. Verification using HDL is too slow to simulate real application programs. This thesis proposes a new design methodology which is called VIP(Verilog Interface for Processor design). Each block is described with C-language and Verilog simulator schedules the blocks. The number of blocks in the microprocessor is only eight blocks, thus scheduling overhead is negligible. The simulation speed of our method is comparable with pure C-language description - all blocks are described with C-language and scheduled by user.
