서지주요정보
슈퍼스칼라 마이크로 프로세서를 위한 연산 유닛과 제어 유닛의 설계 = A design of execution unit and control unit for superscalar microprocessor
서명 / 저자 슈퍼스칼라 마이크로 프로세서를 위한 연산 유닛과 제어 유닛의 설계 = A design of execution unit and control unit for superscalar microprocessor / 박봉일.
저자명 박봉일 ; Park, Bong-Il
발행사항 [대전 : 한국과학기술원, 1996].
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소장정보

등록번호

8006244

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 96029

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초록정보

This thesis covers a design of execution unit and control unit for CISC type superscalar microprocessor. The execution unit has two pipelines. When two RISCore instructions which are simple and pairable instructions are issued, they are executed in each pipeline respectively. An analysis of X86 instruction set usage[11] shows that the usage frequency of the RISCore instructions is about 80%. Even though complex instructions are not pairable, they use both pipelines to reduce execution cycle time. The control unit is designed by microprogrammed approach. The control storage is constructed with two separated ROMs for each pipeline. Design verification is an important part of processor design. Verification using HDL is too slow to simulate real application programs. This thesis proposes a new design methodology which is called VIP(Verilog Interface for Processor design). Each block is described with C-language and Verilog simulator schedules the blocks. The number of blocks in the microprocessor is only eight blocks, thus scheduling overhead is negligible. The simulation speed of our method is comparable with pure C-language description - all blocks are described with C-language and scheduled by user.

서지기타정보

서지기타정보
청구기호 {MEE 96029
형태사항 vi, 48 p. : 삽도 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Bong-Il Park
지도교수의 한글표기 : 경종민
지도교수의 영문표기 : Chong-Min Kyung
학위논문 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과,
서지주기 참고문헌 수록
주제 Microprocessor
Execution
Control
X86
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