The Discrete Cosine Transform(DCT) has been widely used in the image processing and compression. The speed and size of DCT chip is very important for the single chip implementation of HDTV video codec. In this thesis, a 100MHz 14.8㎟ 8×8 2-D DCT chip using distributed arithmetic is implemented. Designing datapath with intensive full custom layout, I try to reduce the area and increase the speed of the chip. The chip is designed with a 0.8μm double metal CMOS technology.
