서지주요정보
저전력 칩상 전압 안정기 설계 = Low-power on-chip voltage generator/regulator design
서명 / 저자 저전력 칩상 전압 안정기 설계 = Low-power on-chip voltage generator/regulator design / 서윤득.
발행사항 [대전 : 한국과학기술원, 1996].
Online Access 원문보기 원문인쇄

소장정보

등록번호

8006217

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 96002

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반납예정일

리뷰정보

초록정보

This paper presents a new on-chip voltage generator/regulator in DRAM with low current consumption. In general, to accomplish a temperature compensation it is necessary to adopt an additional process for the depletion MOS because almost every method obtains the reference voltage from the threshold voltage difference between the enhancement and depletion mode MOSFET. In this paper, a new temperature compensation method is proposed using the concept of so-called 'active bias'. Only using the enhancement mode MOSFET, considerably good performance can be obtained. The total current is less than 5μA at external voltage ranging from 2.5 to 4V and at temperature ranging from 25 to 100℃ the temperature coefficient is about 0.33mV/℃. In addition, dynamic operation method will be introduced, and to implement this approach, a new low-duty-ratio-clock generator will be proposed. Consequently, these methods can be applied to any process and it consumes very low current. So our circuit has an attractive features for the battery-operated high density DRAM's or any other chips.

서지기타정보

서지기타정보
청구기호 {MEE 96002
형태사항 ii, 39 p. : 삽화 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Yoon-Deuk Seo
지도교수의 한글표기 : 박철훈
공동교수의 한글표기 : 김범섭
지도교수의 영문표기 : Cheol-Hoon Park
공동교수의 영문표기 : Beom-Sup Kim
학위논문 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
서지주기 참고문헌 : p. 38-39
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