This thesis presents the design and implementation of Systolic Array type motion estimation processor which adopted Full Search Block Matching Algorithm.
The detectable displacement vector of the designed motion estimation processor is p=-8/+7 and the size of reference block is 8×8 pixels(n=8). The determined search area is 23×23 pixels.
The designed motion estimation processor can search the optimal candidate block for a reference block out of all the possible 256 candidate blocks in the search within 280 pixed cycles and period of one pixel cycle is 80nS(=12MHz). According to this result, we suppose that our motion estimation processor can perform the real-time motion estimation for moving pictures with a frame rate of 30 Hz and 352×288 CIF(Common Intermediate Format) pixel resolution.
The designed motion estimation processor consists of four main functional blocks. The each main functional block is represented in detail and the results of simulation for each functional block are also shown. By top-level simulation, it is verified that the designed motion estimation processor functions OK.
In addition, the architecture for high performance motion estimation processor with 75MHz operating pixel clock for HDTV is proposed.
