Wave pipelining is a timing methodology used in digital systems to achieve maximal rate operation. In this thesis, a 16×16 multiplier is designed and implemented using this technique with only static CMOS gates. To obtain maximum performance, each delay path is balanced so that paths have similar delay times. The circuit has been successfully simulated at 250MHz in a 0.8μm CMOS process, which is 3 times faster than the maximum clock frequency without pipelining.
