서지주요정보
평면형 금속/절연막/다결정실리콘/절연막/금속 안티퓨즈 구조의 금속도선 형성에 관한 연구 = A study on the metal line formation in planar metal/dielectric/poly-Si/dielectric/metal antifuse structure
서명 / 저자 평면형 금속/절연막/다결정실리콘/절연막/금속 안티퓨즈 구조의 금속도선 형성에 관한 연구 = A study on the metal line formation in planar metal/dielectric/poly-Si/dielectric/metal antifuse structure / 정승훈.
발행사항 [대전 : 한국과학기술원, 1995].
Online Access 원문보기 원문인쇄

소장정보

등록번호

8005763

소장위치/청구기호

학술문화관(문화관) 보존서고

MEM 95015

휴대폰 전송

도서상태

이용가능(대출불가)

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반납예정일

리뷰정보

초록정보

The antifuse devices with planar Al/$SiO_2$/Poly-Si/$SiO_2$/Al structure were fabricated using 1.2 ㎛ CMOS process. The poly-Si layer was doped by boron, the thickness of two $SiO_2$ layers was 100Å. The length and the width of the devices were 1.6-18㎛ 1.2-6.0㎛, respectively. The Ⅰ-Ⅴ characteristics of the devices were analyzed using Hewlett Packard 4145B semiconductor analyzer, and the material transport appearance was investigated using optical microscope and scanning electron microscope. The resistance of $SiO_2$ layer was a few giga-ohms and the breakdown voltage of $SiO_2$ layer was 7.6V on the average. After the oxide breakdown, one or two holes were formed on the $SiO_2$ layer and Al flowed through the holes into the poly-Si layer. With further application of voltage after breakdown, Al from one of electrode flowed into the poly-Si layer and reached to the opposite electrode. As a result, two electrodes were connected by a conducting line consist of Al and Si. With the formation of an Al-Si alloy line, the resistance of the device was dropped to nearly 30 ohms, which is much lower than the resistance of poly-Si layer (~kΩ). The direction of Al flow coincided with that of electric field, and the cause of Al flow was supposed to be either $Al^+$ ion conduction or hole migration. After two electrodes are connected, the amount of Al flow decreased rapidly but the width of Al line increased slightly. Above a critical voltage the velocity of Al flow was larger than several cm/sec and below which the velocity was smaller than several tens nm/sec. The critical voltage was proportional to the length of devices ; it meant that the existence of a critical electric current. The measured critical current was about 8mA when the width of the device was 2.4㎛. When a critical voltage was applied without serial resistor to a device with long poly-Si layer, the poly-Si layer is partially melted. This result indicated that the temperature of the devices was very high and current clouding occurred when critical voltage is applied. This could be prevented by attaching serial resistor of larger than a few hundreds ohms. It is supposed that the poly-Si in front of the Al line was partially melted by Joule heating caused by current clouding, when the critical voltage was applied. The melting temperature is supposed to be the eutectic temperature (577℃) of Al-Si, which is much smaller than the melting temperature of pure Si.

서지기타정보

서지기타정보
청구기호 {MEM 95015
형태사항 iv, 64 p. : 삽화 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Sung-Hoon Chong
지도교수의 한글표기 : 안병태
지도교수의 영문표기 : Byung-Tae Ahn
학위논문 학위논문(석사) - 한국과학기술원 : 전자재료공학과,
서지주기 참고문헌 : p. 63-64
주제 Metal oxide semiconductors, complementary.
Breakdown voltage.
Silica.
Scanning electron microscope.
다층막. --과학기술용어시소러스
전류-전압 특성. --과학기술용어시소러스
임계 전압. --과학기술용어시소러스
반도체 소자. --과학기술용어시소러스
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