In a distributed shared memory multiprocessor systems, there must be a cache system for reducing shared memory access latency. In this thesis, we propose a cache controller for SCI-based shared memory multiprocessors. SCI is a IEEE standard(P1596) about interconnections between nodes in the multiprocessor systems.
The proposed cache controller is designed to comprise the multiprocessor system using the general purpose processor. Cache consistency protocol of SCI is supported for implementation of a shared memory. We implement write marking that is proposed in this thesis to reduce write stall.
The proposed cache controller is implemented and verified using VHDL. The results show that write marking can reduce write stall to 80% under no network traffic.
