This thesis covers an implementation of Paging Unit and Cache Unit in K486 microprocessor and proposes a new cache architecture called Separated Word line Decoding(SEWD).
Paging Unit and Cache Unit are designed by full-custom layout and HDL synthesis. For high performance, self-timing logic is used to obtain exact timing signals that control reading and writing and pre-charging. The SEWD can get data that are bounded cache line for only one cycle. Also, this thesis covers a methodology of design and verification of mixed system that consists of full custom blocks and HDL systhesized blocks.