Bias-induced Degradation of Poly-Si TFT was studied for NMOS and PMOS. Channel width and channel length were 30$\mu$m and 5$\mu$m. Bias stress conditions(Vg/Vd) of 30v/10v, 30v/20v, 10v/30v, 20v/30v were used for NMOS and negative values of those were used for PMOS. It is confirmed that charge trapping is negligible in poly-Si TFT with insulating layers of oxide. In NMOS, bias-induced increases of threshold voltage and trap density were observed, which means the creation of defects below $E_F$ in the channel. And for the bias stress conditions of $Vd>Vg$, some additional defects were formed in the drain region above $E_F$ by avalanche. In PMOS, for the bias conditions(Vg/Vd) of -30v/-20v, -30/-10v, magnitudes of threshold voltage and trap density increased, which means that defects are created above $E_F$. And for the bias conditions(Vg/Vd) of -10v/-30v, -20v/-30v, many defects were formed in the drain region below $E_F$ also by avalanche, which decreased leakage current and kink current.
