Image compression techniques are essential for efficient transmission and storage of sequence images. Because of real-time response constraints to decode at the rate of 64 Kbps in the ISDN channel, the hardware add-on digital signal processing(DSP) boards are required to perform the computations. So this thesis describes a cost effective hardware architecture for a 64Kbps Video Codec and implements a Universal DSP Board by using the Mortorola DSP56001 signal processor. After presenting a short review of the CCITT recommended image coding technique, we select a Motion Compensated Interframe Prediction and a Variable Word Length Coding. And implement this selected techniques. This new board is capable of compressing a 112×128 luminance image in real-time. It concludes by presenting some performance measurements and a discussion of the future enhancements.
