Distributed shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. In addition, memory accesses may be cached, buffered, and pipelined to bridge the gap between the slow shared memory and fast processors. Unless carefully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. The set of allowable memory access orderings forms the memory consistency model or event ordering model for an architecture.
This thesis introduces a new model of memory consistency, called Excuse Consistency, that allows for more natural adaptation of buffering and pipelining than previously proposed models. A framework for classifying shared accesses and reasoning about event ordering is developed. The excuse consistency model is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization. Possible performance gains from the less strict constraints of the excuse consistency model are explored.
