A two-dimentional thermoelastic wafer model is proposed to analyze the thermal stress induced slip in silicon wafer during rapid thermal processing.
For the onset of slip in the wafer, the value of the resolved stress on the {111} plane in the <110> slip direction of silicon wafer is compared with the yield stress of silicon which is a function of strain rate, temperature and initial dislocation density. By changing heating rate of the wafer, the wafer temperature at which slip occurs can be increased.
The geometrical distribution of slip line in a (100)-wafer and a (111)wafer is estimated by considering slip plane and slip direction of silicon crystal which has FCC structure. Propagation of the slip line in the wafer is also studied.
