Three dimensional 3-D Poisson's equation solver, KAPOS Ⅲ-B(KAist POisson Solver), was developed to analyze 3-D semiconductor devices. It can handle arbitrary shaped 3-D structure containing silicon region, silicon-dioxide region, metal contact, and free space. This program uses FDM for discretization applied to the integrated form of Poisson's equation, and as a result, implementation of one of the most efficient matrix inversion algorithm, ICCG, was possible. Conductance method and thermionic emission theory were adopted to calculate the current in the linear and subthreshold regions, respectively. Typical simulation CPU-time for conventional MOSFET for a given bias using 30000 grid points is about 10,000 seconds by general-purpose computer HP-9000 (4.7 MIPS).
KAPOS III-B is extensively used to study the drain induced barrier lowering (DIBL) effect in short and narrow MOSFET's, which is experimentally found to become smaller as the device width becomes narrower. Our simulation results can explain successfully this tendency which also becomes much more pronounced as the substrate bias increases. It is shown that the spherical shape of drain depletion region of narrow device is responsible for the reduced DIBL in narrow channel MOSFET's. However, it is found that the breakdown voltage is lowered and the hot-carrier effect increases as the channel width decreases because the electric field becomes stronger near the drain depletion region.
