A BFL NAND gate, which consists of four D FET's and three diodes, was designed and fabricated using mesa-etching for electrical isolation. In this work, the step-coverage problem at mesa-edge was resolved by depositing thin SiO2 film with a thickness of about 200nm to planarize the surface of the mesa pattern, and then forming the gate pattenrn with first metal interconnection. From the measurement of the BFL inverter, the output voltage swing of about 2.1V for the input voltage variation of 3V was obtained. In some case, voltage amplification was found with output voltage swing of 3.6V for input voltage swing of 0.4V. In conclusin, proper operation of BFL NAND gate was confirmed.
