A new technique is proposed for gate level logic simulation and its application to parallel computation for VLSI logic verification. It uses bitwise logic operation and a segmented waveform relaxation method. As the proposed simulator uses bitwise logic operation, the logic waveform of a signal is stored in one bit of word in computer. Although the proposed simulator is based on compiler driven method, the simulator can handle various delay times and multi-valued logic signal which cannot be handled with the compiler driven method. Also, the proposed simulator reduces the memory space and computation time by using the segmented waveform relaxation and effective ordering scheme. When the algorithm is modified for application to computer, about 96% parallism resulted and all kinds of combinational logic circuits could be simulated.
When only one processor is used, the simulator is about one order of magnitude faster than the traditional software event driven simulator. And when a multiprocessor computer is used, simulation speed increases linearly with the number of processors.