The density of integrated circuit (IC) chips is continually on increasing trend. So there have evolved several automatic synthesis systems that aid logic designers in managing the problem.
In this thesis, the synthesis is viewed as the process of transforming Boolean expressions into a standard Transistor Transistor Logic (TTL) IC chip having a list of the products used and a list of the connections to be made between the contact pins of the products. The process is carried out by rules written in Quintus Prolog. We propose module not only having unlimited number of inputs but also being used for representing logic designs which do not depend on specific technology. The synthesis rules are about basic module rules and two-level logic circuit ones having sum of product form. The proposed logic circuit synthesis system is implemented basing on synthesis rules.
For the sake of the verification of logic circuit synthesis system, the synthesized logic circuits are analyzed about functional correctness. The result shows that the implemented logic circuit synthesis system operates correctly.
