In this thesis, a metal gate CMOS Gate Array, named GA1.0, which contains 12 I/O cells and 15 array cells is designed and fabricated. In order to extract the electrical parameters of metal gate CMOS process, CMOS test patterns were fabricated and the model parameters of CMOS which is compatible with SPICE Level 11 MOS transistor model, were extracted. To measure the performance of GA1.0, 11 stage ring oscillator, 9 stage inverter chain and some other circuits were implemented in GA1.0 base. The immunity of the latch-ups were measured by transistor curve tracer. The latch-up occurs with 13 V of supply voltage and snap back to 3 V. The measured input undershoot triggering current (-80 mA) is much smaller than overshoot current (800 mA), which seems to be caused by insufficient $n^+$ guard. The output triggering currents are also measured to be ±40 mA. The switching voltage of array cell and I/O cell inverters are 1.85 and 2.05 V respectively, which agree well with SPICE simulation results. The measured delay times of the array cell from ring oscillator is 41 nsec, which also coincides well with SPICE simulation.
metal gate CMOS process의 전기적 파라메터를 추출하기 위하여 test chip을 설계하고 제작하였다. 추출된 모델 파라미터는 SPICE level II의 MOS 트랜지스터 모델에 맞추었다. metal gate CMOS gate array의 base는 GA1.0으로 이름 지었다. GA1.0에는 15 개의 array cell과 12 개의 I/O cell을 포함하고 있다. GA1.0의 동작을 측정하기 위하여 ring oscillator, nverter chain 등의 test circuit을 제작하였다. 제작된 GA1.0 으로부터 latch up immunity 특성, inverter의 DC 전달 특성 그리고 inverter의 delay time 을 측정하였다.
