Graphene offers great promise to complement the inherent limitations of silicon electronics. As a first step forward to digital logic devices, band gap opening by graphene nanopattering and complementary doping technology provide full swing graphene inverter hiring low off current. Besides, directed self-assembly of block copolymer lithography has proven itself as a cost-effective , parallel, and scalable nanolithography for the densely packed periodic arrays of nanoscale features, whose typical dimension scale in 5 ~ 50 nm is beyond the resolution limit of conventional photolithography.
Herein, we investigated several approach to integrate graphene field effect transistor using directed self-assembly of block copolymer lithography. Multi-channel PDMS/GNR FET and monolithic GNR FET were fabricated by enhanced blockcopolymer softgrapoepitaxy techniques. . In this work, we adopted $OmniCoat^{TM}$ coating and Remover $PG^{TM}$ protocol for SU8 comfinement removal, and residual resist was successfully removed upon monolithic GNR FET. Moreover, we neutrally treated for SU8 confinement vertical surface with polymer bursh, thus blockcopolymer is perpendiculary allinged across the both side confimenment. Compare with last grapepitaxy technique, enhanced process enables to skip hydrophilic treatment of bottom surface to be alligned. Also we implemented mussel-inspired polydopamine adhesive in con-junction with graphoepitaxy principle to tailor graphene nanoribbon array and graphene nanomesh located between metal electrodes. Polydopamine adhesive was utilized for facile and damage-free surface treatment to complement the low surface energy of pristine graphene. Our process minimizes the damage of ideal graphitic structures and electrical properties of graphene during nanopatterning process. Multi-channel graphene nanorib-bon arrays and graphene nanomesh are successfully fabricated between metal electrodes.
To date, considerable research efforts have been devoted to complementary p- and n-type doping of graphene as a fundamental requirement for graphene based electronics. Unfortunately, previous efforts suffer from undesired defect formation, poor controllability of doping level, and subtle environmental sensitivity. Here we present that graphene can be complementary p- and n-doped by simple polymer coating with different dipolar characteristics. Significantly, spontaneous vertical ordering of dipolar pyridine side groups of poly-4-vinylpyridine at graphene surface can stabilize n-type doping at room temperature ambient condition. The dipolar field also enhances and balances the charge mobility by screening the impurity charge effect from bottom substrate. We successfully demonstrate ambient stable inverters by integrating p- and n-type graphene transistors, which demonstrated clear voltage inversion and high gain ($\mid A \mid$) of 0.17 at a 3.3 V input voltage. This straightforward polymer doping offers diverse opportunities for graphene based electronics, including logic circuits.
Additionally, graphene nano mesh FETs toward complementary graphene inverter was successfully fabricated. However, dirac point shift during etch process inhibits typicall inverter performance. After limitation of band gap opening using etch process is overcome by future graphene study, our area-selective polymer doping in conjunction with blockcopolymer nanolithography can accomplish ambient stable graphene inverter that minimize power consumtion.
차세대 그래핀 로직 디바이스의 첫 발걸음을 내딛기 위한 기초소자인 풀스윙이 가능한 저전력 그래핀 인버터는, 나노패터닝에 의한 밴드갭오프닝과 상호보완 도핑기술의 동반개발이 필수적이다. 또한 블록공중합체 리소그래피기술은 일반적인 포토리소그래피기술을 뛰어넘는 5 ~ 50nm의 해상도로서 새로운 고밀집 어레이의 주기적배열을 저비용으로 가능하게 하는 차세대기술로 각광받고 있다.
우선, 나노스케일의 그래핀전계효과트랜지스터를 구현하기 위하여 블록공중합체 리소그래피기술들을 개발하였다. 기존의 블록공중합체 소프트그라포에픽텍시기술을 확장하여 PDMS/그래핀 다중채널 전계효과 트랜지스터와 모노리틱 그래핀나노리본 전계효과 트랜지스터를 제조하였다. 또한 홍합접착제를 블록공중합체 그라포에픽텍시기술과 연계하여 메탈전극사이에 그래핀나노리본과 그래핀나노메쉬를 제조하였다.
두번째로, 그래핀표면에 쌍극자성질을 가진 고분자를 코팅함으로써 상호보완적인 p-도핑과 n-도핑을 구현하였다. 그래핀표면에 코팅된Poly-4-vinylpyridine의 pyridine그룹의 쌍극자가 그래핀표면에 자발적으로 수직배열하기 때문에 상온의 공기분위기에서도 안정적인 n-도핑이 가능하였다. 이러한 고분자 도핑기술을 이용한 상호보완도핑기술은 논리회로와 같은 그래핀 전자회로에 적용가능하다.
마지막으로, 상호보완 그래핀 인버터를 구현하기 위해 그래핀 나노 메쉬 전계효과 트랜지스터를 제조하였다. 불행히도 에칭 프로세스 중 그래핀의 디락 포인트가 시프트하여 일반적인 인버터 성능을 나타내지 못하였으나, 향후 그래핀의 물성을 변화시키지 않는 에칭공정이 개발된다면 본 연구에서 개발된 상호보완 도핑방법과 블록공중합체 나노리소그래피기술은 상온에서 안정적으로 동작가능한 저전력그래핀인버터의 기반기술이 될 수 있다.
