In this thesis, an automatic layout method for CMOS standard cells is considered, which generates mask description in CIF (Caltech Intermidiate Form) from a logic description of a polycell.
Area optimization is achieved by consulting the results of the graph theory and introducing them to the layout compilation of linear transistor arrays.
This layout program is extremely flexible in that it generates both symbolic and physical layout, where the physical layout reflects the design rules and process technology(among N-well, P-well, and Twin-tub) specified by the user at the input file of this program.
A simple consideration to get a plausible W/L ratio between p-channel MOSFET and n-channel MOSFET is given to maintain a reasonable noise margin for each polycell.
Programming was done in C language, and run on MV10000(AOS/VS).
