A set of programs for automatic generation, minimization and verification of high density PLA layout was developed, which includes equation-to-truth table translator, logic minimizer, PLA sorter, file generator for plotting stick diagram, CMOS PLA layout generator, and bipartite row folded CMOS PLA layout generator.
Size reduction is performed mainly by logic minimizer and bipartite row folder, and the maximal delay is reduced by sorter.
The layout file for automatically generated layout is stored in CIF (Caltech Intermediate Form).
Each program was written in C language, and was run on VAX-11/750 (UNIX).