Efficient coding for image data compression is usually achieved by transform. In the transform space, the signal energy is redistributed in such a way that low-order transform coefficients contain most of the picture energy. An optimum transform which compacts most of the energy in the least number of coefficients is KLT. Recent studies demonstrate that DCT is virtually identical to KLT for numerous practical conditions.
Chen, et al. developed a fast algorithm for DCT systematically decomposing the transformation matrix into several matrices each of which contains no more than two non-zero real elements in any row or column.
The objective of this research is to suggest a design method of real-time high-speed FDCT processor which is capable of data compression sufficient to transmit video-conferencing signals via 1.5 Mbps channel.
The effects of limited word length on the computational accuracy of the 16 x 16 2-D FDCT processor is considered. Using 16 x 16 bit array multiplier and 16 bit adder, an FDCT processor with NMSE below -30 dB can be implemented. For the image data with sampling rate of 2 fsc, fsc = 3.579545 MHz, a real-time 2-D FDCT processor can be implemented with two 1-D FDCT processors using four multipliers and as many adders.
A simulation has been performed using the proposed FDCT processor for the Scene Adaptive Coder which is capable of transmitting image signal via 1.5 Mbps channel. There is no visual degradation in SAC using the proposed FDCT with respect to that using real FDCT. The resulting system shows good picture quality at 0.3 bpp.