A common failure mechanism in bulk CMOS integrated circuits is due to the latch-up of the parasitic SCR structure which is inherent from the bulk CMOS structure.
Latch-up triggering and holding characteristics have been measured in test devices which include conventional and Schottky-clamped CMOS structures with various well depth and $n^+ -p^+$ spacings. From the measured results, it is shown that one have to greatly reduce current gains of parasitic bipolar transistors and substrate/well resistances. The current gain of the parasitic lateral pnp transistor in Schottky-clamped structure was about 10 times lower than that in conventional diffused CMOS, and triggering current, holding current and holding voltage of Schottky-clamped CMOS were about 2 times higher than those of conventional diffused CMOS. Therefore Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS.
Finally, the simulation results by circuit simulation program (SPICE) were compared with measured results in order to verify validity of the latch-up model which is composed of two transistors with external resistors.
