In this thesis the code conversion of continuously variable slope delta (CVSD) modulation to and from pulse code modulation (PCM) has been studied with particular emphasis on hardware realization. Specifically, the conversion problem between 64 Kbps PCM with μ-255 companding law and 32 Kbps CVSD with 4 bit syllabic companding law has been investigated.
The study is proceeded in three ways as follows. First, a conversion scheme which has not been studied fully in previous works is suggested with detailed specification Second, the proposed conversion system is simulated on a digital computer to study the system performance. These simulation results show that the system works well and the overall system performance in SQNR is about 20 dB. Lastly, a design scheme for this converter system is suggested in detail. Most important parts of this system are digital filter, compandor and controlling part. In conversion between two signals with different sampling rates, interpolation and decimation filtering are needed. For this purpose a 12-tap Kaiser filter with 8 KHz sampling rate is designed. The arithmatic operation is simplified further with FIR filters than with IIR filters. The companding between linear PCM (LPCM) and compressed PCM (CPCM) signals is done by the digital compandor. In this system a table - look-up method is used as a digital compandor, which can be realized with a ROM and a few IC chips. In addition, a microprogram contained in ROM is used for the system control.
이 논문에서는 PCM 신호와 CVSD 신호의 상호변환에 있어서 새로운 부호변환방식을 연구하였다. 여기서는 일반적으로 쓰이는 μ - 255PCM 과 32 Kbps CVSD 를 다루었다. 먼저 이들 신호간의 상호부호 변환방식을 연구하고 디지탈계산기로 simulation 하여 확인하였으며 이 변환방식을 다지탈회로를써서 설계하고 구성하였다.
이 부호변환방식의 특징은 다음의 네 가지를 들 수 있다. 즉, PCM 신호와 CVSD 신호간의 상호부호변환을 다루었고 이 부호변환기내의 제어신호를 microprogrammed controller 에 의해 발생 시켰다는 점이다. 또 PCM 신호의 Companding 에 있어서 table-look-up 방식을 썼고, FIR filter 를 사용하여 arithmatic operation 을 상당히 줄였다. 특히 이 부호변환기는 Single channel 과 half-duplex mode 의 변환기를 생각하였으며 CVSD 는 single integration 방식을 채택하였다.
