The progresses in integrated circuits and large-scale-integration techniques have made digital systems more complex. It is more difficult to detect a fault from such a system.
In this dissertation a method of test pattern generation for the functional failure in both combinational and sequential circuits by using extended Boolean difference is developed.
This technique provides a systematic as well as an automatic approach for the test pattern generation procedure by computing Boolean difference of the Boolean function of the system for which test pattern is to be generated.
The computer experimental results show that the developed method is proper for both combinational circuits and asynchronous sequential circuits. Suitable models of clocked flip-flops may make it possible to extend this algorithm to synchronous sequential circuits.
Boolean difference 를 이용하여 combinational 論理회로에 생길 수 있는 fault 를 찾는 test pattern 을 구하는 方法을 論하였다. 이것은 asynchronous sequential 회로에도 적용할수 있는 바, 여기서는 feed back 변수를 primary input 로 생각하고, 또한 필요로 되는 homing sequence 를 찾음으로써 해결할 수가 있다.
이러한 方法은 clock 이 있는 SR, D, JK 의 flip - flop을 combinational input 로 적합하게 modelling 하면 synchronous sequential circuit 에도 적용할 수 있음을 보였다.
