A new structure receiver OEIC with a wing-shaped $p^+$-InP layer consisting of an InGaAs/InP PIN photodiode and a self-aligned junction FET has been fabricated using an anisotropically selective etching and a two step OMVPE growth process on semi-insulating InP substrate. The fabrication processes are highly compatible between the photodiode and the JFET. 1.5㎛ hick undoped-InGaAs photo-absorption layer is utilized to achieve reduction in gate length and formation of self-aligned structure in the JFET.
The optical sensitivity of a voltage amplifier type photo-receiver has been calculated in order to understand the parameter specifications of the receiver OEIC. The values of total input capacitance, transconductance of FET and bias resistance are 1 pF, 3 mS and 150 Ω or 2pF, 10mS and 77 Ω respectively, to obtain the sensitivity of -20 dBm at 2 Gbps.
The fabricated OEIC chip has a size of a 600 x 500 $㎛^2$ and cotains four elements: one PIN detector with 80 ㎛ diameter, two JFET's with 2 ㎛ gate length and 150 ㎛ gate width, and one bias resistor of 100Ω made of n-In-GaAs channel layer.
The PIN detector exhibits a leakage current of 2 nA and a capacitance of about 0.35 pF at-5 V bias voltage. An extrinsic transconductance and gate-source capacitance of the JFET are typically 45 mS/mm and 4.0pF/mm at $V_GS$ = 0 V, respectively. The voltage gain of the pre-amplifier is 4.0 at $V_DD$ = 12 V and the bandwidth of the PIN-amplifier OEIC is expected to be about 1.2 GHz. This indicates that this receiver OEIC is capable of detecting a 2 Gbps NRZ signal.
