Clock synchronization in the presence of faults has been studied extensively in recent year in order to increase reliability in real-time systems such as aerospace systems, life support systems, and nuclear power plants. There have been two distinct approaches to the fault-tolerant clock synchronization problem: software-based and hardware-based. It is desirable to use hardware-based clock synchronization scheme for time-critical applications that need tight and reliable clock synchronization.
In this thesis, a new hardware-based clock synchronization scheme and its hardware design are presented. This scheme uses digital clock instead of analog phase-locked clock. Instead of using complex reference clock voting, modified software-based clock synchronization algorithm is used to remedy problems of earlier schemes. Maximum clock skew is first investigated analytically. Second, a method to minimize the clock network in 50% without loss of fault-tolerance is presented.
The functionality of designed circuits and proof of clock synchronization operation in the presence of Byzantine faults are provided by simulation using a logic simulator, Verilog-XL.