서지주요정보
보간기를 이용한 그래픽스 가속기의 구조에 관한 연구 = A study on the architecture of graphics accelerator using interpolator
서명 / 저자 보간기를 이용한 그래픽스 가속기의 구조에 관한 연구 = A study on the architecture of graphics accelerator using interpolator / 배성욱.
발행사항 [대전 : 한국과학기술원, 1992].
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8002492

소장위치/청구기호

학술문화관(문화관) 보존서고

DEE 92010

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In this thesis, we present two special purpose hardwares called EREU (Expandable Rendering Engine Unit) and Patch Renderer respectively, for fast rendering of 3-D scenes. EREU supports continuous shading using Gouraud shading and hidden surface removal using z-buffer algorithm. Each EREU has three major functional blocks: linear interpolator, multipliers and Edge Painting Tree. Linear interpolator with coupled binary tree structure yields the functional values at all pixels within each zone (Zone denotes the smallest interval which encompasses the given span and consists of $2^n$ successive pixels in the x-direction, where n is some integer.) by interpolating the functional values, such as z-depth values or color intensities, at the left and right end points of the zone which are calculated by the multipliers. Mask pattern for the removal of data for the pixels outside the original span but within the corresponding zone is generated by the Edge Painting Tree. Two graphics system architectures having multiple EREU's are proposed, which use the different screen subdivision schemes. The first one adopts the area-based subdivision scheme. This one has advantage in terms of implementation complexity, while it does not suit for high performance system due to its low hardware utilization. For higher performance, the second architecture based on scanline-based subdivision scheme is proposed. The second architecture, called scanline mapped architecture, having 4 EREU's can process 200K 32×10 polygons per second at 40MHz. A prototype graphics system having one EREU has been implemented using 11 FPGA(Field Programmable Gate Array) chips. This PC based system provides 4,096 colors and 680×512 screen resolution, and is able to process 10,000 64×10 polygons per second at 10MHz. Design and logic simulation of EREU chip have been performed using 1.2μ CMOS gate array library but it has not been fabricated yet. Patch Renderer provides more processing power and higher quality images than EREU. Patch Renderer has N VIMU's(Vertical Interpolation and Masking Unit). Since each VIMU processes a span having N vertically consecutive pixels, N×N Patch Renderer can process N×N pixel area called pixel patch at a time. Processing power of each VIMU comes from the bit-serial QIT(Quadratic InTerpolator) which performs the quadratic interpolation of the functional values at all pixels within the given span. Its quadratic feature enables us to use the Fast Phong shading which produces more realistic images than Gouraud shading and to process objects expressed by quadratic equations such as spheres without polygonizing them. Two types of input generators, FIG(Function Input Generator) and MIG(Mask Input Generator), for generating the functional input values and mask input values required by N VIMU's are also included in Patch Renderer. The block mask pattern for removing data within the current pixel patch, but outside the currently processed triangle is generated by Edge Painting Trees in N VIMU's. The estimated performance of one Patch Renderer is 570K Fast Phong shaded triangles per second assuming VLSI implementation. A graphics system having a capability of processing 1 million triangles per second can be implemented using 4 32x32 Patch Renderers.

서지기타정보

서지기타정보
청구기호 {DEE 92010
형태사항 [iii], [86] p. : 삽화 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Seong-Ok Bae
지도교수의 영문표기 : 경종민
지도교수의 한글표기 : Chong-Min Kyung
학위논문 학위논문(박사) - 한국과학기술원 : 전기및전자공학과,
서지주기 참고문헌 수록
주제 Computer graphics.
Acceleration principle.
컴퓨터 그래픽. --과학기술용어시소러스
가속기. --과학기술용어시소러스
Interpolation.
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