This paper proposes a new lowpass filtering scheme. The main goal of the proposed scheme is a tolerance to the process variation and small size. Rather than using one big-tap FIR filter, three small tap FIR notch filters were cascaded to perform lowpass filtering.
The proposed scheme uses only 4 coefficient capacitors. Therefore, coefficient spread can be controlled very small, guaranteeing simulation and measurement consistency. In addition, this new scheme requires very small area because the total number of coefficient is small compared to the traditional one big-tap FIR filters In implementing this filter, major consideration is the integration of analog/RF circuits with digital CMOS logic process. Integrating analog/RF with digital logic is a mandatory for the cost reduction. In this context, switched-capacitor technique is used because of its advantage on deep submicron CMOS technology. Also, process options compatible with only standard digital process are used. Especially, the use of metal-insulator-metal capacitors, which is incompatible with digital logic process, is avoided. Finally, the use of operational amplifiers(op-amp) is also avoided, enabling easy design with imperfect simulation model.
By employing these approaches above, low-cost implementation of analog channel-select filter was possible. The proposed prototype features predictable frequency response under process variation, and compatible with deep-submicron digital CMOS logic process.
