The advancement of device technology, today's scaling down microprocessors, the key components of computers and servers are commercially available with more than 3.4 GHz clock speed. The metal based interconnects on a printed circuit board (PCB), such as bus lines are considered as the bottleneck of the high-speed large data width signal transmission between MPU (Microprocessor Unit) and memories. To alleviate this problem, optical interconnects on PCB has been studied as a promising solutions for replacing the electrical interconnections. As the MPU processing speed increases higher, the electrical interconnects can not support the signal transmission, therefore, next generation computer will adopt optical interconnections. Due to the cost and immature chip-to-chip optical components only high speed data buses between MPU-to-memory will be optically interconnected others low speed buses will remain electrically interconnected. Because of two different interconnections media, the synchronous data between MPU-to-memory will become asynchronous; therefore, a comparison between optical and electrical interconnects for evaluating signal latency is really needed to synchronous again asynchronous data.
In this thesis, signal latency between optical and electrical interconnect is evaluated and to compensate this latency, a signal synchronizing block which can synchronize the asynchronous signal according to clock signal is designed. This synchronizing block is designed by a commercial 0.18-$\microm$ CMOS technology which has been simulated at 5 Gb/s and 0.13-$\microm$ CMOS technology that has been simulated at 10 Gb/s. The synchronizing block exhibits the small dc power consumption of 3.8mW for 1.8 V power supply in 0.18-$\microm$ CMOS technology and 2.09 mW for 1 V power supply in $0.13-\microm$ CMOS technology. The chip size of the block is $590\microm\times560\microm$ in 0.18-$\microm$ technology while $750\microm\times615\microm$ in 0.13-$\microm$ technology.
Another signal synchronizing technique for FPGA system is also presented in this thesis, utilized Hardware Description Language (HDL) and Electronic Design Automation (EDA). Signal Synchronizing block is controlled through a simple but effective algorithm and that is implemented in a Xilinx FPGA chip. A post fit simulation which takes in to account the propagation delay of this particular chip, confirmed that the synthesized hardware is functioning correctly.
