The explosive increase in signal processing speed will cause bandwidth limitations for metal-based interconnects on a printed circuit board (PCB) due to signal attenuation and distortion, electromagnetic interference, crosstalk, and power dissipation. To alleviate this problem, optical interconnects on PCB has been studied as a promising solution due to their advantages such as higher bandwidth, lower power consumption in long distance, EMI free, reduction of impedance matching problem, larger pin density, etc.
The target of this thesis is to design a multi-channel clock and data recovery (CDR) circuit for chip-to-chip optical link applications. Based on the analyses about the advantages and disadvantages of many CDR architectures, the CDR system is proposed using a gated-oscillator-based architecture, which shows good performances, such as fast phase alignment, simple topology, low power dissipation, small chip size, and especially high jitter tolerance.
The key components of the proposed CDR are a charge-pump phaselocked loop (CPPLL), gated-oscillators, and decision circuits. The proposed gated-oscillator has the output frequency's range from 1 to 3.5 GHz, and phase noise equal -90 dBc/Hz at 1 MHz offset frequency. Normally, PLLs used for RF applications are required having a narrow loop filter bandwidth to suppress the phase noise and timing jitter because of the long distant communications and noisy environments. In contrast, the short distant links and less noisy environments in chip-to-chip optical interconnect applications may relax the restriction on the PLL's loop bandwidth. Thus, in the proposed CPPLL, a wider bandwidth loop filter is used; consequently, the CPPLL has faster locking time and smaller chip size.
The proposed multi-channel CDR has the center frequency of gated oscillator around 2.5 GHz; however, the input data rate of each channel can be up to 3.2 Gbps. It consumes 18.27 mW for the CPPLL and 21.21 mW for each channel. The chip size of the CPPLL is 800$\times$750 $\mum^{2}$, while that of each channel is 200$\times$250 $\mum^{2}$ in a 0.18 $\mum$ CMOS technology. The CPPLL is commonly used for all channels; hence, the power consumption and chip size per channel, defined as the total power consumption and total chip size divided by total number of channels respectively, will decrease when the number of channels increases.
Compared to recently published works in this field, the proposed CDR demonstrates some attractive performances, such as power consumption, chip size, and locking time.
