This thesis provides a study on 1.25Gb/s burst-mode receiver design. Firstly, the concept of Passive Optical Network (PON) and the challenges associated with the Optical Line Terminal (OLT) receiver design is addressed in Chapter 1. The fundamental of building blocks in OLTreceiver module, including the transimpedance amplifier (TIA) and the limiting amplifier (LA), is provided in Chapter 2. Besides, the understanding of challenges in burst-mode receiver design is also converted into the fundamental requirement of burst-mode TIA (BM-TIA) and burst-mode LA (BM-LA) blocks in this chapter.
Chapter 3 describes a burst-mode one-chip receiver that support the Ethernet PON (EPON) standard, working without external reset signal. The one-chip receiver uses several new concepts to satisfy burst-mode operation, including burst-based analog AGC, feed-forward topology in differential interface, auto-offset-cancellation in LA blocks, and most importantly the internal reset generation scheme. The design paves the way for new approach in EPON burst-mode receiver design-to create reset signal inside the receiver.
A two-chips version of OLT receiver module is developed in Chapter 4. A BM-TIA using external reset signal is presented. The intention of this design is to make OLT module either from a BM-TIA with external reset signal and a commercial continuous-mode LA or from a BM-TIA and a dedicated BM-LA in which the BM-LA generates reset signal by itself and provide it to the BM-TIA. The design in this chapter focuses on noise and bandwidth optimization of the core TIA circuit, as well as new technique to allow for the use of a BM-TIA with a commercial continuous-mode LA (CW-LA).
Taking advantage of the designs in Chapter 3 and 4, the BM-TIA design in Chapter 5 is set to work alone without requiring external reset signal. The target is to make burst-mode PIN-TIA module that can handle burst-mode traffic by itself, and provide signal that can be AC-coupled to a commercial CW-LA. The BM-TIA in this chapter uses novel concept of selective internal reset generation to deal with bursty signal, and the multi-step AGC to obtain high loud/soft ratio in short response time. Furthermore, with the optimization method from Chapter 4, the BM-TIA can achieve very high sensitivity that allows the ordinary PIN-TIA to cover 20km link specification of EPON. Combining these design techniques, the resultant BM-TIA satisfies both 10km and 20km link specifications. The required guard time and preamble time is also improved significantly with the use of adaptive reset generation scheme. Thanks to the reset, the BM-TIA is capable of running with full range loud/soft ratio from sensitivity to overload levels. With ESD circuit included, the BM-TIA chip is qualified for a commercial chip.
