In the modern wireless communication systems, there are two most popular and well-known architectures. They are heterodyne and homodyne or direct-conversion architectures together with theirs own prominent issues, image problem and flicker noise, respectively. My thesis approach is to deal with each architecture and its own critical problem at the mixer block level.
First, in direct conversion receiver (DCR), flicker noise is a critical issue. For CMOS devices, the flicker noise is high, around 1 MHz of cut-off frequency and 1/f noise tends to corrupt the output base-band signal by degrading the system NF. Therefore, the lower the bandwidth, the higher the degradation is likely to be. Such that, far the narrow band applications like GSM, PCS, the 1/f noise corner frequency needs to be as small as possible since the signal exists at DC after the frequency translation. In this thesis, a 1/f noise-suppression CMOS down-conversion mixer applied in DCR for narrow band applications is designed. The conversion gain is improved by applying the current-reuse bleeding technique in. A critical improvement in flicker noise can be achieved by using an extra inductor. The designed direct-converted mixer achieves a very good performance with the voltage conversion gain of 28.2 dB, SSB NF of 4.09 dB at 5 MHz and 16.8 dB at 50 Hz. 1/f noise cut of Frequency is shifted from nearly 500 kHz to a few kHz. Voltage conversion gain improves more than 4 dB, improvements in flicker noise and white noise are more than 20 and nearly 1 dB, respectively. The proposed mixer is implemented based on 0.18 $\mum$ CMOS technology under a supply voltage of 1.8V supply, and dissipates dc current of 6.3 mA.
Second, in this thesis, a low noise image rejection mixer in heterodyne architecture for 2 GHz applications based on 0.18 $\mum$ CMOS technology is introduced. The designed mixer uses series inductor and capacitors as a notch filter to suppress the image signal and parasitic capacitance to improve the noise figure (NF) and conversion gain. An image rejection of 20-70 dB is obtained in a 200 MHz of bandwidth, from 1.9-2.1 GMz with LO of 1.8 GHz, IF varying from 100 to 300 MHz. With the real component models of TSMC 0.18 $\mum$ technology, the image rejection ratio is from 17.8 to 26 dB, due to the finite Q factor of the inductor. A Small couple of varactors are added in parallel with the inductor for tuning the exact image frequency. The simulation results show single-side band (SSB) NF is improved about 4 dB, the voltage conversion gain of 14.7 dB, improved by around 4 dB. The circuit operates at the supply voltage of 1.8V, and dissipates 12 mW.
