The rapid growth of the market for portable electronic appliances requires flash memory with high performance such as very large storage density, low power consumption and past operation. This high performance was achieved by device scale down. But flash memory has some limitations in device scale down. The tunnel oxide thickness has to more than 8~9 nm due to the basic operation mechanism of flash memory. Nanocrystal memory was proposed for the solution of conventional flash memory scale down limits because this device is more robust to leakage through oxide defects and then has thinner tunnel oxide about 2~3 nm thickness. But the nanocrystal memory still has MOSFET scale down limits due to short channel effects at the device size down to 50 nm.
In this work, Fin-FET nanocrystal memory device was proposed having fin structure with nanocrystal inserted gate stack layer for the real scale down for nonvolatile memory in to the nano-scale era. This structure has nonvolatile memory characteristics due to the nanocrystal memory structure and short channel effect immunity due the double-gate fin structure.
Silicon nanocrystal array, the key part of proposed device was prepared by a low-temperature photo-CVD technique. Si nanocrystals with a high number density and a uniform size distribution were successfully fabricated on a $SiO_2/Si$ substrate by photo-CVD. In this method, hydrogen-diluted radicals have an important role in forming Si nanocrystals. Under conditions of 5 sccm $SiH_4$ and 20 sccm $H_2$, the maximum density was $1.03 \times 10^{12} cm^{-2}$ and the mean size was 5.64 ± 0.54 nm, which enables this method to facilitate nonvolatile memory application. Even at a low temperature of 150℃, Si nanocrystals have a high crystallinity, which was proven from the TEM image. Furthermore, from the CV characteristics, it was shown that the flat-band voltage shift is about 2.89 V at a ±9 V sweep range.
In the photo-CVD, the surface diffusion energy for nanocrystal formation was supplied UV light source. This unique characteristic of photo-CVD was made possible to form silicon nanocrystal on Si fin surface. Fin-FET nanocrystal memory was fabricated using this advantage of photo-CVD and SOI nMOSFET fabrication process. The final fin has 34 nm width and 98 nm height. The thickness of the gate stack layer (tunnel oxide/Si nanocrystal/control oxide) is 14 nm with 100 nm gate length. The saturation current of proposed device was 11 μA/㎛ at Vg-Vth = 1.5 V and Vds = 1.5 V. The threshold voltage is -0.19 V of mean value with 0.05 V of standard deviation value. The subthreshold swing was very good value of 69 mV/dec with 3.85 mV/dec of standard deviation due to the merit of fin structure and drain-induced barrier lowering was about 40 mV/V.
Both case of writing and erasing, as increasing amount of stress i.e. increasing amplitude and duration of stress pulse threshold voltage shift increased. Fin-FET nanocrystal memory device after write/erase with ± 13 V, 0.5 sec at Vds = 0.1 V has about 1.5 V threshold voltage shift. From the retention measurement of the Fin-FET nanocrystal memory with a write and erase voltage, the 80% of charge remained at 104 sec and the 26% of charge are expected at 10 years.
The proposed Fin-FET nanocrystal memory device has both the characteristic of Fin-FET structure and nonvolatile memory characteristics of nanocrystal memory structure. And this device was believed that the solution of flash memory scale down and performance improvement.
