This paper proposes a new methodology to check the consistency between the user requirement specification and a DEVS (Discrete Event System Specification) model being developed.
There was a research on the development of discrete event simulator that enables a domain expert to communicate with a modeling expert by using UML (Unified Modeling Language) diagram. In the development method, the user requirement specification about a target system in natural language is transformed in UML diagrams, and a model expert develops a DEVS model using the diagrams. However, development of a large and complex simulator should require ensuring consistency
between the user requirement specification and a DEVS model in order to guarantee that the simulator being developed meets the specified requirements. In this paper we propose a new method to assist the consistency verification of a discrete event simulation model, specified by DEVS formalism, against user requirement specification, expressed in natural language.
A classic sequence diagram in UML has a limit in expressing an interrupt event. In addition there is no specific guidance to write the user requirement specification. Therefore some information which is necessary for a DEVS model is omitted or ambiguous. We solve these problems by extending an expression power of a classic sequence diagram and designing a new template for the user requirement
specification.
Our approach is composed of successive steps of consistency verification between the user requirement specification and a DEVS model. The first step is the validity check of UML diagrams against the user requirement specification. We also propose an improvement in a development method of a DEVS model. The second step is verification of event sequences between an UML diagram and a DEVS model.
The proposed verification method has been implemented in an automated tool named VERIDEVS. Inputs to VERIDEVS are UML diagrams and DEVS Graph, both of which are graphical representation in Visio, and outputs are verification tables in PowerPoint. VERIDEVS consists of a drawing element parser, an activation composer, a state composer, a sequence generator, and a sequence comparator. The drawing element parser analyzes basic drawing elements of input diagrams. The activation composer and the state composer reconstruct an input diagram from outputs of a drawing element parser. The sequence generator and the sequence comparator execute verification of event sequences between an UML diagram and a DEVS model.
To demonstrate effectiveness of the proposed methodology, a modeling and consistency verification of a Warship model which is firing torpedoes is exemplified across the paper.
본 논문에서는 사용자 요구사항과 개발된 이산사건 모델 사이의 일관성을 검증하는 방법론을 제안하였다. 검증 방법은 세 단계로 나누어지며, 첫 번째와 두 번째 단계는 UML 다이어그램과 사용자 요구사항 간의 일관성 검증이다. 세 번째 단계는 DEVS 모델과 UML 다이어그램의 이벤트 시퀀스를 검증한다. 제안한 검증 방법을 자동으로 수행할 수 있는 환경인 VERIDEVS를 구현하여 검증 과정을 자동화하였다. VERIDEVS의 입력은 Visio로 도식되는 UML 다이어그램과 DEVS 그래프가 되고, 자동 검증 결과는 PowerPoint를 이용하여 제안하는 검증 테이블의 형태로 출력된다. 제안한 검증 방법과 자동 검증 환경의 효용성을 입증하기 위하여 실제 해군 워게임 모델에서 사용되었던 대잠수함 교전 시뮬레이터의 예를 들어 자동 검증을 수행하였다.
