Noise performance of electronic circuits principally such as time-invariant circuits is usually handled in the frequency-domain rather than in the time-domain due to the simple noise expressions and calculations in the frequency-domain. However, according to the increase in the complexity of the circuit architecture and in the demand on the transient analysis of time-variant circuits, several studies on the time-domain noise analysis have been attempted in spite of the difficulty in the modeling and simulation of the noise signals in the time-domain.
In this study the Monte Carlo based time-domain Hspice noise simulation with random amplitude piecewise waveform and its application to a design of low-noise CMOS readout circuits were evaluated. The amplitude distribution of thermal noise was modeled with Gaussian random number. In case of 1/f noise, since its amplitude distribution is a non-Gaussian one, its waveform was modeled with several serial-connected low-pass filters of thermal noise generators with cascaded poles. These time-domain noise sources were connected in parallel with the drain and source nodes of the CMOS input transistor of the preamplifier. The Hspice transient noise simulation of a CSA-CRRC circuit with these noise sources yielded ENC values at the output node of the shaper for thermal and 1/f noise of 47 e- and 732 e-, respectively. ENC values calculated from the integral of the transfer function in the frequency-domain are 44 e- and 882 e-, respectively. The results of the Hspice transient noise simulation were similar to those of the frequency-domain calculation. To validate this time-domain noise simulation, a test chip was designed and fabricated in the AMI 0.5 μm CMOS technology. The measured ENC value was 904 e-. These results show that the Monte Carlo based time-domain noise simulation is valid.
The technique obtained from this time-domain noise simulation was applied to a design of a multi-channel readout circuit for CdZnTe detector arrays. The shot noise of detector leakage current and the thermal and 1/f noise of input transistor were modeled in the time-domain with the data provided by the vendor. One channel of the readout circuit is comprised of a preamplifier and a comparator. The optimal geometry of the input transistor was obtained by using the Hspice transient noise simulation. The simulated RMS noise voltage of the preamplifier output was 0.246 mV. A prototype chip was fabricated in the AMI 1.5 μm low-noise analog CMOS process and the measured RMS noise voltage of the preamplifier output was 0.435 mV. This value is much smaller than that of the trip voltage of the comparator’s hysteresis. The results suggest that this Monte Carlo based Hspice transient noise simulation could give circuit designers an insight for the design of low-noise electronic circuits and could be an effective tool for the design of those circuits.
