This paper describes proposed PLL structure that make PLL more insensitive to process variation. There are many papers about low noise PLL, low jitter PLL, fast locking (short locking time) PLL, high frequency oscillating PLL and applications of PLL. But the effect of PLL by process variation is also critical problem. VCO in PLL is very sensitive to process variation. VCO output frequency to control voltage characteristic graph moves up and down by the effect of process variation. PLL may not lock and locking point may be out of linear range by process variation, so diligently designed PLL could be useless only because this phenomenon. When we design PLL, consideration about process variation should be done. I will compensate the phenomenon by process variation using divider that have variable divider value. Divider value could be changed adaptively to the condition.
PLL is designed and simulated by TSMC 0.18$\mu$m CMOS technology.
