The Paion PPII network processor is designed to meet the growing need for new high bandwidth communication equipment targeted for internet routers and ethernet adapters. In order to rapidly reconfigure the processor for frequently varying internet services and technologies, a high performance C compiler is urgently needed. Albeit various code generation techniques have been proposed for complex instruction set DSPs or ASIPs, we experienced these techniques are not easily tailored towards the target Paion PPII processor due to striking architectural differences. First, we will show the architectural challenges posed by the target processor. Second, novel compiler techniques will be described that effectively exploit unorthogonal architectural features. The techniques include virtual data path, compiler intrinsics, and interprocedural register allocation. Third, intermediate benchmark results will be presented to demonstrate the effectiveness of our techniques. The results show that our techniques can be frequently applied to significantly reduce the dynamic instruction counts.
