The ferroelectric material $SrBi_2Ta_2O_9$ (SBT) has been extensively investigated for integrating nonvolatile ferroelectric random-access memories (FeRAM). However, it has been made clear over the past few years that electrodes play a major role in determining the device properties and performance. In some cases, the effect of the electrode brings about modifications of the microstructure of the ferroelectric film and in some cases, the electrode directly controls the properties of the SBT capacitor.
An SBT layer must be annealed in oxygen ambient after deposition. This immediately limits the choice of electrodes, particularly those for the bottom electrodes. In this sense, platinum (Pt) is one of the most promising candidates for the bottom electrodes of ferroelectric thin film. However, the adhesion of platinum to substrates such as silicon-oxide ($SiO_x$) is poor. Thus, titanium (Ti) glue layer has typically been used.
The Pt/Ti electrode stack deposited by the sputtering method tends to have a major instability problem, i.e., Pt hillock formation. Pt hillocks are a major concern because they can lead to short-circuit-failure of capacitor. The hillock formation depends strongly on the compressive stress generated during both deposition and post-annealing. Three factors are considered in the total stress generated during both deposition and post-annealing in Pt/Ti electrode stack: intrinsic stress, thermal stress and extrinsic stress. Among them, the intrinsic stress and the extrinsic stress are very important in device integration since the stress values can be easily adjusted with the process parameters and sequence.
Therefore, we studied the stress dependency of hillock formation observed on the Pt surface during post thermal cycling. Titanium layer was deposited at 200℃. But, the deposition temperature of the platinum layer was varied from room temperature (RT) to 500℃ to control the initial stress of the as-deposited film stacks. And then, the Pt/Ti film stacks were annealed at various temperatures between RT and 650℃, and in different ambients (oxygen and nitrogen). Two types of hillock were observed after the post thermal treatment at 650℃ for 30min in oxygen ambient: pyramidal hillock and plateau hillock. The morphological changes that took place on the Pt surface by the heat treatment were well understood by monitoring the stress evolution during the heat treatment.
The pyramidal hillock was observed on the Pt surface deposited at room temperature. And, the hillocks were decreased in both number and height with increasing the deposition temperature of the Pt layer. It was revealed in both SEM inspection and stress measurement that the deposition temperature dependence of the Pt hillock formation could be explained by the difference of the initial stress condition after platinum deposition. The pyramidal hillock was nucleated at the temperature about 300℃~400℃ for relaxing the compressive stress generated by both intrinsic stress and thermal stress. And, the nucleated hillock was grown to large high hillocks by the extrinsic compressive stress generated at the temperature around 450℃~550℃. The height of the fully grown pyramidal hillocks was over 1000Å, and the grains were (100) preferred orientation in contrast of the (111) preferred orientation in the as-deposited Pt films.
The effect of pyramidal hillocks on electrical properties of SBT capacitor was also evaluated. The thickness of SBT layer and that of the top electrode platinum layer was about 1500Å and 2000 Å, respectively. The measured capacitor size was 50 μm × 50 μm. The platinum layer was deposited at high temperature of 500℃ for suppressing the pyramidal hillock formation. The high temperature deposition of the platinum layer decreased the short-circuit-failure probability of the SBT capacitor to nearly 0% from 100% of the capacitor fabricated on the platinum layer deposited at room temperature. In contrast, the 2Pr values of the SBT capacitors were nearly same about 13 μC/㎠ regardless of the Pt deposition temperatures. The leakage current density was also nearly same of about $5 × 10^{-8} A/㎠$.
By the way, the platinum surface deposited at 500℃ was still observed platinum hillocks. The shape of the hillocks was plateau-like and the preferred orientation was (111) direction, in contrast with the pyramidal hillock. And the height of the plateau hillocks were below 500Å. The titanium was started to diffuse into the platinum layer at the temperature about 400℃. The high compressive stress was generated by the titanium diffusion into the platinum layer followed by oxidation in the platinum grain boundaries at the temperature over 400℃. The compressive stress was the major driving force for the plateau hillock formation. The platinum grains were extruded toward the surface by the high compressive stress field.
Thus, the titanium glue layer was oxidized before platinum deposition by annealing at 650℃ for 30 min in oxygen ambient to reduce the titanium diffusion into the platinum layer. The Pt/$TiO_x$ electrode stack retained its smooth platinum surface after the electrode annealing of 650℃ for 30 min in oxygen ambient. The Pt/$TiO_x$ interface remained flat even after the ferroelectric crystallization annealing at 800℃, which was performed after $SrBi_2Ta_2O_9$ (SBT) deposition.. That is, the plateau hillock formation could be suppressed by using the TiOx glue layer instead of titanium glue layer.
1500-Å-thick SBT layer was deposited on the Pt/$TiO_x$ electrode stack to evaluate the effects of plateau hillock on the electrical properties of the capacitor. And 2000-Å-thick platinum layer was deposited on SBT layer as top electrode. The measured capacitor size was 100 μm × 100 μm, which was larger than that used in evaluating the pyramidal hillock effects. The short-circuit-failure probability of the SBT capacitor was decreased to about 50% on the Pt/$TiO_x$ electrode stack from about% in the SBT layer coated on Pt/Ti film stack. Moreover, the remanent polarization (2Pr) of the SBT capacitor was increased to 17 μC/㎠ on the Pt/$TiO_x$ electrode stack, up from 13 μC/㎠, which was the value on the Pt/Ti electrode stack. The titanium diffusion into the SBT layer may directly affect the electrical properties of SBT. However, the titanium amount in the SBT layer was nearly 0% in AES analysis regardless of the electrode stack. By the way, the SBT layer on the Pt/$TiO_x$ electrode stack was shown to change denser microstructure than that of the SBT layer coated on Pt/Ti electrode stack. So, it was thought the denser microstructure was the major reason of the polarization improvement on the Pt/$TiO_x$ electrode stack.
