InP/InGaAs heterojunction bipolar transistors (HBTs) are one of the best candidates for ultra high frequency digital, analog and mixed signal integrated circuits due to their inherent material properties. The techniques of reducing parasitic elements, especially base resistance and base-collector capacitance, have been important fabrication issues for more improved high frequency characteristics of HBTs. In this work, various techniques of reducing base resistance and base-collector capacitance of InP/InGaAs HBTs have been studied and discussed. In addition, also new methods for reducing base resistance and base-collector capacitance are investigated in this thesis.
A novel self-alignment technique has been proposed and developed for minimizing base resistance. The new self-alignment technique, which utilizes crystallo-graphical wet etching characteristics of the InP material, can make a T-shaped emitter electrode. The T-shaped emitter electrode provides reliable contact spacing between the emitter and the base electrode without over-etching of the emitter mesa. The proposed self-alignment technique is expected to be very useful for fabricating submicron size emitter HBTs with the conventional optical lithography. The method can also be used in fabricating self-aligned gate-source (drain) MESFET and HFET. The fabricated DC device ($5\times30\mum^2$ emitter size) with the T-shaped emitter electrode showed DC current gain $h_{FE}$ of 20, offset voltage $V_{CE,offset}$ of 130mV, collector ideality factor $n_C$ of 1.02 and base ideality factor $n_B$ of 1.08.
In order to reduce the extrinsic base-collector capacitance, a new base pad design has been also proposed and demonstrated. The new layout is based on lateral etching characteristics of InGaAs (or InP) with different crystal-orientation. The isolation between the base pad and the intrinsic device region can be easily achieved without any additional etching step by the proposed base pad design. The new layout method is expected to be very useful for improving the high frequency performance of the scaled-down small area SHBTs and DHBTs. Two devices, fabricated using the proposed base pad isolation technique (I-HBT) and the conventional method (C-HBT), were compared to investigate the effects of the base pad isolation. The fabricated I-HBT using the conventional self-align process showed the common-emitter characteristics such as the offset voltage $V_{CE,offset}$ of 150mV and the collector-emitter breakdown voltage $BV_{CEO}$ of 5.7V. The DC current gain $h_{FE}$ of 19 was obtained with the ideality factors of $n_C$ = 1.05 and $n_B$ = 1.34. The frequency response of the fabricated device was measured on-wafer from 0.5GHz to 18GHz using an 8720C Network Analyzer. Due to the frequency limit of the measurement setup, S-parameter fitting and parameter extraction were performed using a small signal model to estimate the accurate frequency characteristics of the fabricated device. The results of S-parameter fitting show excellent agreement between measured and calculated data. The maximum $f_T$ and $f_{max}$, estimated by -20dB/decade extrapolation from the measured current gain ($h_{21}$) and unilateral power gain (U), were found to be 72 and 242 GHz, respectively. The extracted values of the base resistance ($R_b$) and base-collector capacitance ($C_{bc}$) were 6.9Ω and 7.2fF, respectively. The I-HBT shows 20% improvement (198GH→242GHz) of peak $f_max$. The effective $Rb\cdotC_{bc\cdoteff}$ products for the I-HBT and C-HBT, estimated from the relationship of $f_{max}$=$[f_T/(8\piR_bC_{bc})]^{1/2}$, were found to be 49fs and 67fs, respectively. A 27% decrease(67f→49fs) in the time delay of $R_b\cdotC_{bc\cdoteff}$ is directly attributed to the associated decrease in the extrinsic base pad.
