Mobile systems such as PDA and cellular phone are very popular. Such a mobile system requires lower power VLSI chip. The VLSI chip needs low power ROM (Read Only Memory), especially for digital filters and signal processors. Bit lines in the ROM core dissipate most of the power because bit lines have large capacitance and a lot of bit lines are selected per an access. Also, the predecoder outputs connected to a lot of main decoder are long and high-capacitive lines. As the ROM size increases, the predecoder lines dissipate power significantly. In order to reduce these power consumptions, a charge-recycling predecoder (CRP), a charge recycling ROM (CR-ROM), and a charge sharing ROM (CS-ROM) are proposed.
The CRP reduces the power dissipated in the predecoder lines by recycling the charge stored in a previously selected predecoder line to a newly selected predecoder line. Ideally, the CRP saves half of the dissipated power. Although size and power overhead of the control logic exists, the overhead is small and independent of predecoder line capacitance size. The simulation result shows that the CRP consumes less power than the convention predecoder and the saved power approaches 50%, as the capacitance of the predecoder line increases.
The CR-ROM reduces the power consumption of ROM bit lines using the charge recycling method. With this method, power consumption in ROM bit lines can be reduced asymptotically to zero if the number of bit lines is infinite and the sense amplifiers detect infinitely small voltage difference. However, the real sense amplifiers cannot sense very small voltage difference. Therefore, the reduction of power consumption is limited. The CR-ROM saves power significantly in bit line, but all bit lines in the CR-ROM consume the power for the charge recycling operation in every cycle even if the bit lines are unnecessary. So, when the larger number of bit lines is selected, the CR-ROM is more efficient. The simulation results show that the CR-ROM achieves up to 19% power consumptions but requires about 2.7 times more area than the conventional low power contact programming ROM.
The CS-ROM also reduces the power consumption of ROM bit lines using the charge sharing method. The voltage swing in the bit lines can be reduced to the minimum input voltage difference of the sense amplifier by a controllable dummy capacitance. Although the saved power in each bit line of the CS-ROM is smaller than the CR-ROM, only selected bit lines dissipate power while all bit lines dissipate power in the CR-ROM. The simulation results show that the CS-ROM only consumes 32% ~ 57% of the conventional low power contact programming ROM and the size of the CS-ROM is the same as that of the conventional diffusion programming ROM. The CS-ROM is the best choice when both power and area are considered.
All circuit simulation and chip fabrication are based on 0.25um CMOS process parameters and HSPICE models. Parasitic capacitances and resistances are included in the simulations. Powers are measured at 100MHz clock frequency with VCC = 2.5V.
