In this thesis, a CMOS process using impurity diffusion is designed and evaluated. In order to evaluate this CMOS process, CMOS test patterns are fabricated and the model parameters, which are compatible with SPICE level 2 MOSFET parameters, are extracted. The threshold voltages, mobilities and subthreshold slopes of the fabricated devices are measured as 1.16V, 670.8 ㎠/Vsec, 116.4 mV/dec for NMOS and -1.28V, 205.7 ㎠/Vsec, 88.7 mV/dec for PMOS. Using this CMOS process, a test readout circuit for measurement of 240×4 HgCdTe diode characteristics is fabricated, and the expected operation of a decoder in the readout circuit is confirmed by measurement. And a driving circuit for 40×40 flat panel display is fabricated.
