Digital signal processors (DSP) are specialized for high performance numerical algorithms used in communication and voice processing. But the existing DSPs are insufficient to process multimedia data with video sequences. Since visual information such as video sequences or images yields a large amount of data rate, image data have to be compressed to transmit these image data through a wire and a wireless channel in real time. Specially, video compression algorithm calls for heavy and complex computation power. So DSP architecture for moving picture coding needs to have the specific architecture to exploit the ILP (Instruction Level Parallelism) and execute multiple operations simultaneously. Superscalar and VLIW (Very Long Instruction Word) architecture can take advantage of this parallelism. The Texas Instruments TMS320c62x has VLIW DSP architecture capable of issuing eight operations in parallel.
H.263 is based on techniques common to many other current video-coding standards. So H.263 includes essential functional blocks in moving picture coding. Therefore, implementation of H.263 codec on TMS320c6201 DSP chip is good for a starting point in development of new DSP architecture for efficient moving picture coding by grasping problem of previous commercial DSP.
This thesis describes an implementation procedure of H.263 codec with TMS320c6201 DSP chip and proposes improvement scheme for video signal processor. To improve the execution speed of H.263 codec, we optimized H.263 codec with various techniques at three design phases including algorithm level, C-code based implementation level and assembly-code based implementation level. In assembly-code based implementation level, we utilized architectural features of TMS320c6x such as eight-issue VLIW architecture and control bit, and optimized the utilization of internal memory. Finally, we have achieved a reasonably high encoding speed of 8 frames per second for CIF and that of 20 frames per second for QCIF. And analyzing the H.263 coder in a development process, we propose several new instructions and an architecture scheme to make TMS320c62x more efficient for video compression application. The proposed SIMD (single instruction multiple data) instruction can be used to improve the performance of motion estimation and interpolation. And the proposed scheme solves the memory alignment problem occurring during the data communication between internal and external memory.
