In this thesis, an asymmetric ATM multicast switch fabric with quasi-shared buffering is implemented using six Xilinx field programmable gate arrays (FPGAs). The switch fabric has a switch size of 8×16 and operates at a speed of 20MHz. An internal test signal generator is also implemented at the same printed circuit board and is utilized to verify its operations for unicast cells, multicast cells and empty cells. This FPGA implementation result can be utilized in designing the application specific integrated circuit (ASIC) chips of the ATM switch architecture.
