As the time to market pressure and product complexity increase, it becomes harder for a designer to complete the overall system design in time. Therefore, there are many researches towards reducing the total design time by reusing IP(Intellectual Property). If there is no IP which follows the protocol of the target system, a designer must make an interface module which converts protocols between IP and the bus of the target system. In this case, making an interface module between IPs' with different protocols is tedious and error prone task. Automatic interface module generation between them will solve that problem and reduce the total design-time.
We describe an algorithm to generate an interface module between two synchronous hardware modules with different protocols and clock frequencies. The algorithm accepts port-information, module names, two protocols, and connection-information as input, and generates an RTL interface module in Verilog HDL. The algorithm reduces the input-description overhead by automatic generation of the slave-side protocol from the master-side protocol. If a designer describes the protocol of IP as master's view, the protocol as slave's view will be derived automatically. This reduces time in making the interface module between two busses with different protocols. This thesis proposes S-STG(Synchronous Signal Transition Graph) to describe a protocol. S-STG can be obtained from a timing diagram and information on control signals. Compared with other formalisms, S-STG reduces the difficulties in describing a protocol. An interface module has two controllers each of which is used to control the communication with connected external module. Synchronization of two controllers is achieved by local and global synchronization. Separation of two controllers makes it possible to generate an interface module automatically between two modules that communicate with external devices with different frequency. Two S-STG are converted to two FSMs' automatically. Resulting interface module is an RTL module in Verilog HDL.
Verification of the algorithm proposed in this thesis is achieved by simulation. Two examples demonstrate the effectiveness of this algorithm.
