서지주요정보
고속 Row-cycle이 가능한 VPM(virtual pipelined memory) 구조에 대한 연구 = A study on VPM(virtual pipelined memory) architeture for a fast row-cycle DRAM
서명 / 저자 고속 Row-cycle이 가능한 VPM(virtual pipelined memory) 구조에 대한 연구 = A study on VPM(virtual pipelined memory) architeture for a fast row-cycle DRAM / 윤치원.
발행사항 [대전 : 한국과학기술원, 1999].
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등록번호

8009768

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 99084

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초록정보

In this paper, we presented the system level performance analyzer, POPeye and compared the performance of VCM and SDRAM. VCM showed the higher performance for various applications than that of SDRAM's about 20%. Also we proposed VPM(Virtual Pipelined Memory), a new DRAM Architecture with fast Row-cycle using Top-down approach with POPeye. VPM has VCM's channel structure and its background operations are optimized by high level simulation with POPeye. Fast row-cycle is possible by adopting pipeline structure at row path. Row buffer below the sense amp. and inserted latch at the output of address decoder consists of the pipeline stage. VPM has backward compatibility with conventional memory system in a view of interface and also consumes less power by partial activation of Cell Core. The performance of VPM is higher than that of SDRAM about 40% and VCM about 20%.

서지기타정보

서지기타정보
청구기호 {MEE 99084
형태사항 [v], 71 p. : 삽화 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Chi-Won Yoon
지도교수의 한글표기 : 유회준
지도교수의 영문표기 : Hoi-Jun Yoo
학위논문 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
서지주기 참고문헌 : p. 70-71
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