For the high-speed, low power consumption, and small silicon area, the datapath has been designed by full custom approach in the commodity microprocessor chip. As the design complexity increases, the datapath compiler which generates the compact layout has been used both for ASIC and cost-performance microprocessor design to improve the design productivity.
In this thesis, the new approaches and algorithms for the high-performance datapath compiler are proposed: such as placement, buffer sizing, interconnect design, track assignment, and layout schemes. To examine the performance of these approaches, 'real-world' examples from the several complex microprocessors are used for the experiment.
In determining the optimal datapath placement a hybrid approach of genetic algorithm(GA) and simulated annealing(SA)is applied to minimize both the track density and the wire length. To improve the computation speed, we utilize the good initial population generation heuristics and datapath-specific genetic operators. Experimental results show that our hybrid approach outperforms the existing genetic approaches and gives similar results to the simulated annealing using only 44% of the computation time of SA.
The traditional datapath compiler generates the same-sized buffers for all bits. Considering the bit-by-bit difference of load capacitance in real designs, the bit-wise buffer sizing scheme is proposed. This scheme leads to the balance of the bit-wise delay and the power minimization. According to the experiments, the power consumption of the tri-state driver for the long running bus can be minimized as much as 43% by the bit-wise buffer sizing scheme.
As the CMOS technology enters into deep submicron design era, the inter-wire cross-coupling effect gives large impact on the performance. The iterative interconnect sizing method considering the cross-coupling effect is suggested with experimental data based on 0.25μm technology. An effective control signal ordering scheme considering the cross-coupling effect minimizes the power consumption by 10% and the delay by 15%. A new track assignment algorithm considering the switching behavior based on the evolutionary programming is proposed to minimize the cross-coupling effect. Using these effective interconnect methodologies, we can improve the chip performance by 40%.
Finally, three layout schemes, two dimensional transistor placement, the vertical ploy positioning, and the micro-level floorplan mixing the regular and irregular bit cell, are proposed for the compact module generation and easy technology migration. Using these schemes, we can improve the datapath compactness by 30% compared to the traditional datapath compiler.
