Recently there are many researches of much integrated and low power communication systems because of the needs of personal communication using cheap CMOS technology instead of expensive technologies, such as Biploar and GaAs. The circuits of base band part are much integrated, but those of RF input part are not integrated, so in this paper the frequency synthesizer for PCS application, which is most important RF input part, is implemented using 0.8um CMOS technology.
The frequency synthesizer is designed using proposed offset PLL architecture. The most important parts of frequency synthesizer are Voltage-Controlled Oscillator(VCO) and prescaler. The VCO is designed using multiple-nested feedback and replica biasing, and the voltage-clamped source-decoupled delay cell of VCO is proposed, which increases oscillation frequency because of small parasitic capacitor and small output swing. The source-folded-diode-clamping ECL-like D flip-flop is proposed, which increases input maximum frequency and decrease the power dissipation because the equivalent sampling time is increase and the input buffer that enlarges the input signal is removed. New prescaler is proposed using multiple-nested architecture, which increase maximum input frequency.
The frequency synthesizer is implemented using 3.3V single supply, so maximum oscillation frequency of proposed VCO is 1.8GHz at 3.3V and 2.1GHz at 5V, and maximum input frequency of proposed prescaler using multiple nested feedback is 5GHz.
