There has been many trials to implement a 2-D DCT/IDCT processor via the 1-D row column decomposition method. On the contrary this paper proposes a new architecture based on a direct 2-D DCT/IDCT algorithm. The proposed architecture is especially suitable for a small area low bit rate video codec in wireless multimedia services as well as high speed application. The proposed scheme is scalable and easy to implement. DCT/IDCT processor having the proposed architecture has been implemented using VHDL, and its performance has been evaluated by C-language simulation program. The simulation results shows that the proposed architecture is prospective for DCT/IDCT operation in low bit rate coding.